1. Field of the Invention
This invention is concerned with sub-unit and memory communications in a data processing system that uses a multibyte width system bus, which system is microprocessor implemented. More particularly, this invention is directed to improving the performance of such communications where the multibyte system bus is interfaced with the system under the control of a microprocessor having insufficient control information output lines to form a required command byte for the system bus in a single system cycle.
2. Description of the Prior Art
The emulation of "main frame" data processing systems through the use of microprocessors has become a reality. A typical main frame data processing system would be any one of the System 370 (S/370) models available from International Business Machines Corporation. The PC/XT370, a "desktop" System 370, also available from International Business Machines Corporation, is one example of such a microprocessor implemented main frame. This particular desktop system is a hardware/software package that allows one to run S/370 application programs in a single user environment, to run as a terminal attached to a main frame host or to run in a stand-alone mode, as required by the particular application. There are, of course, similar systems available from other manufacturers, all of which systems incorporate many of the same functions as the PC/XT370 although the manner and means of implementation does differ, in varying degrees, from system to system.
Due to revolutionary advances in chip densities and packaging, which have been accompanied by significant reductions in costs, many main frame features can now be implemented directly in a desktop system, while other features require some hardware and/or software assistance in order to make them available. The introduction and use of more powerful microprocessors such as, for example, the 8086 and 8088 from Intel Corporation and the 68000 from Motorola Corporation, added further to the list of functions it would be possible to implement in a desktop mainframe. This new breed of microprocessors is fully capable of running a large, enriched instruction set, such as that of S/370, although several of these microprocessors working in concert with the aid of additional hardware and/or software support, would be required to effect instruction execution in an acceptable time period.
As in all data processing system designs, various trade-offs are made in order to optimize the price and performance of these desktop mainframes. One particular trade-off problem is posed by the need or desire to utilize certain mainframe functions and features that would be particularly difficult to provide in a microprocessor implemented desktop mainframe. One specific implementation problem of concern is that of accommodating the word and bus width differences between a mainframe central processing unit (CPU) and a microprocessing unit (MPU). In the System 370 world, for example, the system bus will be of multibyte width to accommodate the wider words employed therein. The use of a multibyte width system bus permits the transmission of greater amounts of data and control information in each system cycle which enhances system performance. Usually, one of the plurality of system bus bytes is a command byte, the constituent bits of which are used to indicate, among other things, the type of command to be undertaken by a sub-unit, including memory, that is attached to the bus. Unfortunately, that arrangement of a multibyte width system bus will pose a problem when accommodated in the microprocessor implemented desktop mainframe, since current microprocessors do not have the requisite bus command output information immediately available. That information will, therefore, have to be provided in another manner.
The simplest and possibly most convenient manner of providing command byte information is to write an appropriate command byte to a memory mapped register and then gate this register to the system bus once access thereto is granted. However, implementation of this approach would require an extra cycle in order to write to the command register, after the command byte had been read from memory, each time a command byte was needed for any purpose. That performance penalty would significantly offset the benefits of using a high data transfer rate bus. Thus, while it would be possible to readily accommodate the use of a command byte and multibyte width system bus in a microprocessor implemented desktop main frame, the performance penalty associated with a memory mapped solution thereto is too great to accept.